1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, it relates to a semiconductor memory device having a structure capable of supplying a stable power supply voltage.
2. Description of the Prior Art
The structure of a conventional semiconductor memory device 9000 is described with reference to FIG. 20. The semiconductor memory device 9000 shown in FIG. 20 has an internal circuit group 990 including memory cells and a synchronous circuit 995 generating an internal clock. The synchronous circuit 995 is driven by an operation start trigger signal and generates the internal clock deciding operation timing in the internal circuit group 990. The synchronous circuit 995 is formed by a PLL circuit or the like, for example.
As shown in FIG. 20, the synchronous circuit 995 and the internal circuit group 990 share a power source 900, to operate with a power supply voltage received from the power source 900 and a ground voltage GND as operating voltages.
The operating voltages must be stable so that the synchronous circuit 995 performs a synchronous operation in high precision.
When the internal circuit group 990 operates, however, noise originates following current consumption to disadvantageously swing the power supply voltage. In the structure of the conventional semiconductor memory device 9000, therefore, precision of the internal clock is disadvantageously damaged following the internal operation.
When the internal circuit group 990 is defective, the power supply voltage or a signal voltage similarly swings. Therefore, influence following a failure of the internal circuit group 990 must be suppressed not only for circuits in the same chip but also for another device connected through the same wire.